The present invention relates to providing increased data access speed in computer memories without increasing the basic clock rate of the memory.
Terminology
Throughout this description the following terms are used:
DIMM=Dual In line Memory Module
SDRAM=Synchronous Dynamic Random Access Memory.
DDR=Double Data Rate. Data bit duration equals one half the period of the clock frequency. Two bits of data are used in one period of the base clock. See FIG. 1(b).
DBR=Double Bus Rate.
SDR=Single Data Rate.
DBF=Data Bit Frequency. The number of bits per second per pin. Referred to as xx bit/sec/pin.
DR =Data Rate. The Data Bit duration equal to one period of the base clock. See FIG. 1(a)
Definition: Double Bus Rate (DBR)
For the purpose of description through out this document, the term DBRTM (Double Bus Rate) will be used. Double Bus Rate means that the Data Rate. out of and into a BUS system will be double of what each individual chip connected to the BUS delivers at its operating clock frequency. PRIOR ART
The desire for increased throughput in a memory subsystem requires that the memory devices perform at higher speeds. Normally, a memory chip of the single data rate type SDR operating at a certain base frequency will produce data rate DR of one period of the base frequency. A DR of 100 MHz means that the duration of each data bit will be equal to one period of the 100 MHz frequency which is equal to 10 nanoseconds. The data bit pulse- width coming out of the DRAM chip will be one period of the base clock. Therefore, as shown in FIG. 1(a), the actual frequency of any data bit alternating between 1 and 0 when the base clock is 100 MHz is 50 MHz.
As it pertains to the memory chip packaging configuration used today, in order to meet a desired DATA BUS width, a cluster of memory chips, such as SDRAMs, are assembled together on a printed circuit board. (The smallest bus-width is the actual number of bits coming out of a single SDRAM chip in a cluster of one). These boards are configured in several forms, known as SIMMs, DIMMs, SODIMMs, RIMMs, etc. However, for the sake of brevity, the term DIMM will be used hereinafter to refer to any or all of these different types.
The prior art DIMM module of 168 pins, (the design applies to any D o of any other pin count, or any other package known by any other name), currently uses (as defied by the JEDECxe2x80x94Joint Electron Device Engineering Counselxe2x80x94Committee) 72 Data bits bus, Control lines, Address lines, Power and Clocks. The present modules as defied by the JEDEC standard can accommodate up to two Banks or Rows of SDRAM chips. Other configurations of banks are also used depending on the system architecture. The selection of the Banks is controlled by a single Chip Select (CS) line or a combination of the Chip Selects and other control lines. The DIMM module is either a Register or NonRegister configuration. In a Register configuration all the Address and Control lines are latched into a Register first before they are presented to the devices to be selected for operation In a Non-Register configuration the Address and Control lines are wired directly from the input tabs of the DIMM to the devices. Either configuration can have a Phase Locked Loop (PLL) for clock synchronization or utilize the clock presented to the DIMM by the system. As shown in FIG. 1(a), with a clock of 100 Mplz for the base operating frequency of the memory chip, the module can only produce a maximum DR of 100 MHz. If the clock frequency is raised to 133 MHz, and the SDRAM devices on the DJMM operate at 133 MHz, the maximum DR is increased to 133 MHz. In order to achieve 200 MHz DF, the SDRAM chips must operate at the base frequency of 200 MHz. To have SDRAM chips operate at higher frequencies requires development dollars, time and improvements in silicon speed and processing. Density and speed interfere with each other, When the density increases, the speed decreases simply because many levels of interconnection are required for the circuitry and thus more delay is introduced to the circuit path. Also the implementation of high speed and high density within the silicon becomes very difficult, and in some cases, prohibitive.
In prior art designs of the DIMM utilizing SDRAM devices operating at 100 MHz clock rates, the design is easily implemented with the commonly used Printed Circuit Board (PCB) physical properties and line widths. Therefore, designing a DIMM memory module with base clock frequency of 100 MHz is quite simple to produce with the current technology. The problem appears when one is trying to produce devices that operate at 200 MHz base clock frequency.
Referring now to FIG. 2A, it is seen that, in the prior art, two identical memory chips 100, 102, are controlled by the same 100 MHz clock at clock input A 104, and clock input B 105. The single bit output 106 of chip A is connected to the corresponding output 107 of chip B. Only one chip is allowed to operate at any given time with the other chip isolated to high impedance by internal chip circuitry at the outputs 106, 107. The Chip Select (CS) input of Chip A 120 allows Chip A to access the data, and the corresponding input 121 does the same for chip B. This architecture is the basis for building DIMM modules with prior art.
Both of the chips above are operating from the same clock. The data bit at pin D 102, 106 will either come from chip A or chip B. Referring now to FIG. 2(b), the clock which appears at the input pin of chip A 104 and chip B 105 has a 100 MHZ frequency. A typical clock cycle begins at t1 with an positive-going signal, and ends at t2, 10 nanoseconds later. A typical data signal, shown as FIG. 2(c), is synchronized with the data signal, so that a data xe2x80x9conexe2x80x9d condition begins at t1, and ends at t2, while the following data xe2x80x9czeroxe2x80x9d begins at t2 and ends at t3. It should be noted that the highest bandwidth data signal which be processed by this system is one with alternating ones and zeros. Still referring to FIG. 2(c), it is seen that such a data signal has a frequency of one-half the clock frequency, although the data rate, measured in bits per second, is the same as the clock rate
As a result, the highest data rate DR delivered to a memory bus of the prior art system is equal to the data rate that the memory chips A or chips B can deliver by design.
The JEDBC group has developed an architecture wherein one bit of data has duration of validity equal to one half the period of the base clock frequency. This scheme is called DDR for (Double Data Rate). A DIMM designed with such SDRAM devices is called DDR DIMM. Although such DDR memories are currently in existence, they require memory chips operating at twice the clock frequency. Such high speed memory chips are expensive and difficult to produce.
Referring now to FIGS. 1(a) through 1(c), the rates of the various signals described herein are shown. Referring now to the first such waveform, a 100 MHz clock is shown FIG. 1(a), together with a typical data bus signal (a single bit only is shown for illustrative purposes) of the prior art DIMM, in FIG. 1(b). Each data bit begins in synchronism with a positive-going edge t1 of the clock signal. This waveform is typical of the SDR configuration of the prior art.
In comparison, the DDR data bus of the prior art operates at twice the SDR rate. Referring now to FIG. 1(c), each data bit of the DDR data signal begins with either the positive-going edge t1 of the clock signal, or the negative-going edge t12 of the clock signal.
Presently, the devices used incorporate a 100 MHz base clock frequency, and a 100 MHz Data Bit Frequency of the DUR type. For the purposes of this description these devices will be called SDRAM DDR devices (100,100). The current invention will disclose a system which produces 400 MHz DR and 200 MHz Data Bit Frequency utilizing SDRAM chips (100,100). This system is called the Double Data Rate/Double Bus Rate (DDR/DBR) system.
Using the technique of the current invention described herein, a DR of 400 MHz, or 200 MHz DBF is produced at the data bus using a 100 MHZ clock frequency. Using the prior art, in comparison, the fastest speed achievable with existing SDRAM devices is the speed of the SDRAM device itself. By using the techniques described herein, however, existing SDRAM devices, whether SDR or DDR, will produce double the device""s DR on the data bus. See FIGS. 1(c)-(f)
It is the general object of the current invention to provide a DDR memory architecture using SDR memory chips. It is a further object of this invention to combine DDR memory chips to provide a quad-speed output.
In accordance with one aspect of the current invention, a computer memory system with a data bus includes a first bank memory bank with data lines; a second memory bank having data lines; and a clock signal having a multiplicity of cycles, each having a start, and a period p; In addition, the system includes a first switching means to connect the data lines of the first memory bank with the data bus beginning at the start of each cycle, and lasting for a time p/2, and a second switching means to connect the data lines of the second memory bank with the data bus beginning at p/2 after the start of each cycle, and lasting for a time p/2 thereafter.
In accordance with a second aspect of the invention, the computer memory system also includes a delayed clock signal at a phase 180 degrees relative to the clock signal, with the second switching means synchronized with the delayed clock signal.
According to a third aspect of the invention, the system includes a motherboard, and the means to generate the delayed clock signal, the first memory bank, the second memory bank, the first switching means, and the second switching means are all located on the mother board.
According to a fourth aspect of the invention, the system includes one or more DIMM boards, and the means to generate the delayed clock signal, the first memory bank, the second memory bank, the first switching means, and the second switching means are located on the DIMM boards.
According to a fifth aspect of the invention, the first switching means includes first FET switch, the second switching means includes a second FET switch.
According to a sixth aspect of the invention, the first FET switch includes a control input, a first side connected with the data bus, and a second side connected to the data lines of the first memory bank. In addition, the second FET switch further includes a control input, with a first side connected with the data bus, and a second side connected to the data lines of the second memory bank.
According to a seventh aspect of the invention, the first switching means includes a first data enable signal operating on a first memory chip, and the second switching means includes a second data enable signal operating on a second memory chip.
According to an eighth aspect of the invention, the system also includes a circuit having an input and an output, with the input connected to the clock signal, and the delayed clock signal the output, selected from the group which consists of wire length delay circuits, skewed output driver delay circuits, cascaded PLLs delay circuits, skewed output PLL delay circuits, external to PLL delay circuits, passive element delay circuits, and programmed delay lines.
According to a ninth aspect of the invention, a computer memory system having a data bus, includes a first bank memory bank having data lines, a second memory bank having data lines, and a clock signal having a multiplicity of cycles, each having a start, and a period p. It also has a first switching means to connect the data lines of the first memory bank with the data bus beginning at the start of each cycle, and lasting for a time p/4, and starting again at p/2 after the start of each cycle, and lasting for a time p/4. It further has a second switching means to connect the data lines of the second memory bank with the data bus beginning at p/4 after the start of each cycle, and lasting for a time p/4, and starting again at 3p/4 after the start of each cycle, and lasting for a time p/4.